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Si5540
P R E L I M I N A R Y D A TA S H E E T
SiPHY TM OC-192/STM-64 TRANSMITTER
Features
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated 16:1 multiplexer and DSPLLTM based clock multiplier unit: Data Rates Supported: OC-192/STM-64, 10GbE, and 10.7 Gbps FEC Low Power Operation 0.6 W (typ) Small Footprint: 99-Pin BGA Package (11 x 11 mm) OIF SFI-4 Compliant Interface Output Clock Powerdown Operates with 155 or 622 MHz Reference Sources Optional 3.3 V Supply Pin for LVTTL Compatible Outputs Single 1.8 V Supply Operation
Si5364
DSPLLTM Based Clock Multiplier Unit w/ selectable loop filter bandwidths
Bottom View
Applications
Sonet/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Optical Transceiver Modules Sonet/SDH Test Equipment
Ordering Information: See page 17.
Description
The Si5540 is a fully integrated low-power transmitter for high-speed serial communication systems. It combines high speed clock generation with a 16:1 multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based on Silicon Laboratories' DSPLLTM technology which eliminates the external loop filter components required by traditional clock multiplier units. In addition, selectable loop filter bandwidths are provided to ensure superior jitter performance while relaxing the jitter requirements on external clock distribution subsystems. Support for data streams up to 10.7 Gbps is also provided for applications that employ forward error correction (FEC). The Si5540 represents a new standard in low jitter, low power and small size for 10 Gbps serial transmitters. It operates from a single 1.8 V supply over the industrial temperature range (-40C to 85C).
Functional Block Diagram
R EFSEL R EFC LK 2 R EFRATE TXC LK16IN TXLOL BW SEL TXC LKD SBL TXCL KOUT TXDOU T 2 16:1 MUX FIFO 2 R eset Con trol D SPLL TM CMU 2 2 32
/ 16
TXCL K16OU T
TXCL K16IN TXDIN [15:0] FIF ORST
B ias
R EXT
RES ET
F IFOER R TXSQLC H TX M SBSEL
Preliminary Rev. 0.31 8/01
Copyright (c) 2001 by Silicon Laboratories
Si5540-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si 5540
2
Preliminary Rev. 0.31
Si5540 TA B L E O F CONT E N TS
Section Page
4 9 9 9 9 10 10 10 11 12 14 17 18 20
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si5540 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.31
3
Si 5540
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature LVTTL Output Supply Voltage Si5540 Supply Voltage Symbol TA VDD33 VDD Test Condition Min* -40 1.71 1.71 Typ 25 -- 1.8 Max* 85 3.47 1.89 Unit C V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated.
V SIGNAL + Differential VICM, VOCM I/Os SIGNAL - VIS Single Ended Voltage
(SIGNAL +) - (SIGNAL -) Differential Voltage Swing VID,VOD (VID = 2VIS) Differential Peak-to-Peak Voltage t
Figure 1. Differential Voltage Measurement (TXDIN, TXDOUT, TXCLK16IN, TXCLK16OUT)
tsu TXDOUT, TXDIN
thd
tCH TXCLKOUT, TXCLK16IN
tCP
Figure 2. Data to Clock Delay
All Differential IOs tF tR
80% 20%
Figure 3. Rise/Fall Time Measurement
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Preliminary Rev. 0.31
Si5540
Table 2. DC Characteristics, VDD = 1.8 V
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current Power Dissipation Common Mode Output Voltage (TXDOUT,TXCLKOUT) Differential Output Voltage Swing (TXDOUT,TXCLKOUT), Differential pk-pk LVPECL Input Voltage High (REFCLK) LVPECL Input Voltage Low (REFCLK) LVPECL Input Voltage Swing (REFCLK), Differential pk-pk LVPECL Input Common Mode (REFCLK) Input Impedance (REFCLK, TXDIN, TXCLK16IN) LVDS Input High Voltage (TXDIN, TXCLK16IN) LVDS Input Low Voltage (TXDIN, TXCLK16IN) LVDS Input Voltage, Single Ended pk-pk (TXDIN, TXCLK16IN) LVDS Input Common Mode Voltage (TXDIN, TXCLK16IN) LVDS Output High Voltage (TXCLK16OUT) LVDS Output Low Voltage (TXCLK16OUT) LVDS Output Voltage, Single Ended pk-pk (TXCLK16OUT) LVDS Output Common Mode Voltage (TXCLK16OUT) Output Short to GND (TXCLK16OUT, TXDOUT, TXCLKOUT) Output Short to VDD (TXCLK16OUT, TXDOUT, TXCLKOUT) LVTTL Input Voltage Low (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET)
IDD PD VOCM VOD VIH VIL VID VICM RIN VIH VIL VISE VICM VOH VOL VOSE 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line, See Figure 1 Each input to common mode See Figure 1
-- -- .8 800 1.975 1.32 250 1.65 42 -- 0.0 100 .8 TBD 0.925 250
333 0.6 0.9 1000 2.3 1.6 -- 1.95 50 -- -- -- 2.0 -- -- 400
TBD TBD 1.0 1200 2.59 1.99 2600 2.30 58 2.4 -- 600 2.4 1.475 TBD 550
mA W V mV (pk-pk) V V mV (pk-pk) V
V V mV (pk-pk) V V V mV (pk-pk) V mA
A
VOCM ISC- ISC+ VIL2
1.125 -- TBD --
1.20 25 -100 --
1.275 TBD -- 0.8
V
Preliminary Rev. 0.31
5
Si 5540
Table 2. DC Characteristics, VDD = 1.8 V (Continued)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Voltage High (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET) Input Low Current (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET) Input High Current (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET) Input Impedance (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET) LVTTL Output Voltage Low (FIFOERR, TXLOL) LVTTL Output Voltage High (FIFOERR, TXLOL)
VIH2
2.0
--
--
V
IIL
--
--
10
A
IIH
--
--
10
A
RIN
10
--
--
k
VOL2 VOH2
VDD33 = 1.8 V VDD33 = 3.3 V VDD33 = 1.8 V VDD33 = 3.3 V
-- -- 1.4 2.4
-- -- -- --
0.4 0.4 -- --
V V
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Si5540
Table 3. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TXCLKOUT Frequency TXCLKOUT Duty Cycle Output Rise Time (TXCLKOUT, TXDOUT) Output Fall Time (TXCLKOUT, TXDOUT) TXCLKOUT Setup to TXDOUT TXCLKOUT Hold From TXDOUT Output Return Loss TXCLK16OUT Frequency TXCLK16OUT Duty Cycle TXCLK16OUT Rise & Fall Times TXDIN Setup to TXCLK16IN TXDIN Hold from TXCLK16IN TXCLK16IN Frequency TXCLK16IN Duty Cycle TXCLK16IN Rise & Fall Times
fclkout tch/tcp, Figure 2 tR tF tsu thd Figure 3 Figure 3 Figure 2 Figure 2 400 kHz-10 GHz 10 GHz-16 GHz fCLKIN tR, tF tDSIN tDHIN fCLKIN tch/tcp, Figure 2 tR, tF Figure 2 tch/tcp, Figure 2
-- 45 -- -- 25 25 TBD TBD -- 40 100 -- -- -- 40 100
9.95 -- 25 25 -- -- -- -- 622 -- -- -- -- 622 -- --
10.7 55 -- -- -- -- -- -- 667 60 300 300 300 667 60 300
GHz % ps ps ps ps dB dB MHz % ps ps ps MHz % ps
Table 4. AC Characteristics (Clock Multiplier Characteristics)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Generation--Deterministic Jitter Generation--Random Jitter Transfer Bandwidth
JDET(PP) JGEN(RMS) JBW
PRBS-23
-- --
0.020 0.005 -- -- 0.05 15 622 155 -- --
TBD TBD 12 50 0.1 20 667 167 60 100
UIPP UIRMS kHz kHz dB ms MHz MHz % ppm
BWSEL = 0 BWSEL = 1
-- -- --
Jitter Transfer Peaking Acquisition Time Input Reference Clock Frequency TAQ RCFREQ Valid REFCLK REFRATE = 1 REFRATE = 0 Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance RCDUTY RCTOL
-- -- -- 40 -100
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Preliminary Rev. 0.31
7
Si 5540
Table 5. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k)
VDD VDD33 VDIF
-0.5 to 3.0 -0.5 to 3.6 -0.3 to (VDD+ 0.3) 50
V V V mA C C C V
TJCT TSTG
-55 to 150 -55 to 150 275 TBD
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Symbol JA Test Condition Value Unit
Thermal Resistance Junction to Ambient
Still Air
35
C/W
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Preliminary Rev. 0.31
Si5540
Functional Description
The Si5540 is a fully integrated, low power, SONET/ SDH transmitter for OC-192/STM-64 applications. It combines a high performance clock multiplier unit (CMU) with a 16:1 serializer that has a low-speed interface compliant with the Optical Interface Forum (OIF) SFI-4 standard. The CMU uses a phase-locked loop (PLL) architecture based on Silicon Laboratories' proprietary DSPLLTM technology. This technology is used to generate ultralow jitter clock and data outputs that provide significant margin to the SONET/SDH specifications. The DSPLL architecture also utilizes a digitally implemented loop filter that eliminates the need for external loop filter components. As a result, sensitive noise coupling nodes that typically cause degraded jitter performance in crowded PCB environments are removed. The DSPLL also reduces the complexity and performance requirements of reference clock distribution strategies for OC-192/STM-64 optical port cards. This is possible because the DSPLL provides selectable wideband and narrowband loop filter settings that allow the user to set the jitter attenuation characteristics of the CMU to accommodate reference clock sources that have a high jitter content. Unlike traditional analog PLL implementations, the loop filter bandwidth is controlled by a digital filter inside the DSPLL and can be changed without any modification to external components. bandwidth is selected via the BWSEL control input. In traditional PLL implementations, changing the loop filter bandwidth would require changing the values of external loop filter components. In narrowband mode, a loop filter cutoff of 12 kHz is provided. This setting makes the Si5540 more tolerant of jitter on the reference clock source. As a result, the complexity of the clock distribution circuitry used to generate the physical layer reference clocks can be simplified without compromising jitter margin to the SONET/SDH specification. In wideband mode, the loop filter provides a cutoff of 50 kHz. This setting is desirable in applications where the reference clock is provided by a low jitter source like the Si5364 Clock Synchronization IC or Si5320 Precision Clock Multiplier/Jitter Attenuator IC. This allows the DSPLL to more closely track the precision reference source resulting in the best possible jitter performance.
Reference Clock
The CMU within the Si5530 is designed to operate with reference clock sources that are either 1/16th or 1/64th the desired output data rate. The CMU will support operation with data rates between 9.9 Gbps and 10.7 Gbps and the reference clock should be scaled accordingly. For example, to support 10.66 Gbps operation the reference clock source would be approximately 167 MHz or 666 MHz. The REFRATE input pin is used to configure the device for operation with one of the two supported reference clock submultiples of the data rate. The Si5540 supports operation with two selectable reference clock sources. The first configuration uses an externally provided reference clock that is input via REFCLK. The second configuration uses the parallel data clock, TXCLK16IN, as the reference clock source. When using TXCLK16IN as the reference source, the narrowband loop filter setting may be preferable to remove jitter that may be present on the data clock. The selection of reference clock configuration is controlled via the REFSEL input. The Si5540 will drive the TXLOL output high to indicate the DSPLL has locked to the selected reference source.
DSPLLTM Clock Multiplier Unit
The Si5540's clock multiplier unit (CMU) uses Silicon Laboratories' proprietary DSPLL technology to generate a low jitter, high frequency clock source capable of producing a high speed serial clock and data output with significant margin to the SONET/SDH specifications. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. Therefore, SONET/SDH jitter compliance is easier to attain in the application. Programmable Loop Filter Bandwidth The digital loop filter in the Si5530 provides two bandwidth settings that support either wideband or narrowband jitter transfer characteristics. The filter
Serialization
The Si5540 includes serialization circuitry that combines a FIFO with a parallel to serial shift register. Low speed data on the parallel input bus, TXDIN[15:0], is latched into the FIFO on the rising edge of TXCLK16IN. The data in the FIFO is clocked into the
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Preliminary Rev. 0.31
Si 5540
shift register by an output clock, TXCLK16OUT, that is produced by dividing down the high speed transmit clock, TXCLKOUT, by a factor of 16. The TXCLK16OUT clock output is provided to support 16 bit word transfers between the Si5540 and upstream devices using a counter clocking scheme. The high-speed serial data stream is clocked out of the shift register using TXCLKOUT. Input FIFO The Si5540 integrates a FIFO to decouple data transferred into the FIFO via TXCLK16IN from data transferred into the shift register via TXCLK16OUT. The FIFO is eight parallel words deep and accommodates any static phase delay that may be introduced between TXCLK16OUT and TXCLK16IN in counter clocking schemes. Further, the FIFO will accommodate a phase drift or wander between TXCLK16IN and TXCLK16OUT of up to three parallel data words. The FIFO circuitry indicates an overflow or underflow condition by asserting FIFOERR high. This output can be used to recenter the FIFO read/write pointers by tieing it directly to the FIFORST input. The Si5540 will also recenter the read/write pointers after the device's power on reset, external reset via RESET, and each time the DSPLL transitions from an out of lock state to a locked state (TXLOL transitions from low to high).
Parallel Input To Serial Output Relationship
Clock Disable
The Si5540 provides a clock disable pin, TXCLKDSBL, that is used to disable the high-speed serial data clock output, TXCLKOUT. When the TXCLKDSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to 1.5 V through 50 on-chip resistors. This feature is used to reduce power consumption in applications that do not use the high speed transmit data clock.
Bias Generation Circuitry
The Si5540 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 3.09 k (1%) resistor connected between REXT and GND.
The Si5540 provides the capability to select the order in which data on the parallel input bus is transmitted serially. Data on this bus can be transmitted MSB first or LSB first depending on the setting of TXMSBSEL. If TXMSBSEL is tied low, TXDIN0 is transmitted first followed in order by TXDIN1 through TXDIN15. If TXMSBSEL is tied high, TXDIN15 is transmitted first followed in order by TXDIN14 through TXDIN0. This feature simplifies board routing when ICs are mounted on both sides of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the network, the Si5540 provides a control pin that can be used to force the high speed data output, TXDOUT, to 0. By driving TXSQLCH low TXDOUT will be forced to 0.
Reset
A device reset can be forced by holding the RESET pin low for at least 1 s. When RESET is asserted low, the input FIFO pointers reset and the digital control circuitry initializes. When RESET transitions high to start normal operation, the DSPLL will be calibrated.
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Preliminary Rev. 0.31
Si5540
Differential Output Circuitry
The Si5540 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications where direct dc coupling is possible, the 250 nF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5.
1.5 V
VDD 50 250 nF Zo = 50
50
50
250 nF
Zo = 50
50
VDD 24 mA
Figure 4. CML Output Driver Termination (TXCLKOUT, TXDOUT)
Preliminary Rev. 0.31
11
Si 5540
Si5540 Pinout: 99 BGA
10
9
8
7
6
5
4
3
2
1
TXDIN[12]-
TXDIN[12]+
TXDIN[14]-
TXDIN[14]+
REFCLK-
REFCLK+
TXSQLCH
RSVD_ VDD33
REFRATE
A
TXDIN[10]+
TXDIN[11]+
TXDIN[13]-
TXDIN[13]+
TXDIN[15]-
TXDIN[15]+
TXCLKDSBL
REFSEL
RSVD_ VDD33
GND
B
TXDIN[10]-
TXDIN[11]-
GND
GND
GND
GND
RESET
VDD33
GND
TXCLKOUT+
C
TXDIN[8]+
TXDIN[9]+
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
TXCLKOUT-
D
TXDIN[8]-
TXDIN[9]-
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
GND
E
TXDIN[6]+
TXDIN[7]+
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
TXDOUT+
F
TXDIN[6]-
TXDIN[7]-
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
TXDOUT-
G
TXDIN[4]+
TXDIN[5]+
GND
GND
GND
GND
GND
BWSEL
NC
GND
H
TXDIN[4]-
TXDIN[5]-
TXDIN[3]+
TXDIN[3]-
TXDIN[1]+
TXDIN[1]-
TXMSBSEL
RSVD_ GND
TXLOL
REXT
J
TXDIN[2]+
TXDIN[2]-
TXDIN[0]+
TXDIN[0]-
TXCLK16 IN+
TXCLK16 IN-
TXCLK16 OUT+
TXCLK16 OUT-
FIFORST
FIFOERR
K
Bottom View
Figure 5. Si5540 Pin Configuration (Bottom View)
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Preliminary Rev. 0.31
Si5540
1
2
3
4
5
6
7
8
9
10
A
REFRATE
RSVD_ VDD33
TXSQLCH
REFCLK+
REFCLK-
TXDIN[14]+
TXDIN[14]-
TXDIN[12]+
TXDIN[12]-
B
GND
RSVD_ VDD33
REFSEL
TXCLKDSBL
TXDIN[15]+
TXDIN[15]-
TXDIN[13]+
TXDIN[13]-
TXDIN[11]+
TXDIN[10]+
C
TXCLKOUT+
GND
VDD33
RESET
GND
GND
GND
GND
TXDIN[11]-
TXDIN[10]-
D
TXCLKOUT-
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
TXDIN[9]+
TXDIN[8]+
E
GND
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
TXDIN[9]-
TXDIN[8]-
F
TXDOUT+
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
TXDIN[7]+
TXDIN[6]+
G
TXDOUT-
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
TXDIN[7]-
TXDIN[6]-
H
GND
NC
BWSEL
GND
GND
GND
GND
GND
TXDIN[5]+
TXDIN[4]+
J
REXT
TXLOL
RSVD_ GND
TXMSBSEL
TXDIN[1]-
TXDIN[1]+
TXDIN[3]-
TXDIN[3]+
TXDIN[5]-
TXDIN[4]-
K
FIFOERR
FIFORST
TXCLK16 OUT-
TXCLK16 OUT+
TXCLK16 IN-
TXCLK16 IN+
TXDIN[0]-
TXDIN[0]+
TXDIN[2]-
TXDIN[2]+
Top View
Figure 6. Si5540 Pin Configuration (Transparent Top View)
Preliminary Rev. 0.31
13
Si 5540
Pin Descriptions: Si5540
Pin Number(s)
Pin Name
I/O
Signal Level
Description Bandwidth Select DSPLL. This input selects loop bandwidth of the DSPLL. BWSEL = 0: Loop bandwidth set to 12 kHz BWSEL = 1: Loop bandwidth set to 50 kHz. FIFO Error. This output is driven high when a FIFO overflow/underflow has occurred. This output will stick high until reset by asserting FIFORST. FIFO Reset. This input, when asserted high, resets the read/ write FIFO pointers to their initial state. GND.
H3
BWSEL
I
LVTTL
K1
FIFOERR
O
LVTTL
K2
FIFORST
I
LVTTL
B1, C5-8, C2, D8, D2, E8, E1-2, F8, F2, G8, G2, H4- 8, H1 H2
GND
GND
NC
--
No Connect. Reserved for device testing; leave electrically unconnected.
A5-6
REFCLK+, REFCLK-
I
LVPECL
Differential Reference Clock. The reference clock sets the operating frequency of the PLL used to generate the output clock frequency. The Si5540 will operate with reference clock frequencies that are either 1/ 16th or 1/64th the output clock rate. Reference Frequency Select. This input configures the CMU to operate with one of two possible reference clock frequencies. When REFRATE = 1, the CMU will operate with a reference that is 1/16th the output clock rate. When REFRATE = 0, the CMU will operate with a reference that is 1/64th the output clock rate. Reference Clock Selection. This inputs selects the reference clock source used by the CMU. When REFSEL = 0, the low speed data input clock, TXCLK16IN, is used as the CMU reference. When REFSEL = 1, the reference clock provided on REFCLK is used. Device Reset. Forcing this input low for at least 1 s will cause a device reset. For normal operation, this pin should be held high.
A2
REFRATE
I
LVTTL
B3
REFSEL
I
LVTTL
C4
RESET
I
LVTTL
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Preliminary Rev. 0.31
Si5540
Pin Number(s) Pin Name I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor.
J1
REXT
D3, E3, F3, G3, J3 A3, B2 K5-6
RSVD_GND RSVD_VDD33 TXCLK16IN-, TXCLK16IN+ TXCLK16OUT+, TXCLK16OUT-
-- -- I LVDS
Reserved Tie to Ground. Must tie directly to GND for proper operation. Reserved Tie to VDD33. Must tie directly to VDD33 for proper operation. Differential Data Clock Input. The rising edge of this input clocks data present on TXDIN into the device. Divided Down Output Clock. This clock output is generated by dividing down the high speed output clock, TXCLKOUT, by a factor of 16. It is intended for use in counter clocking schemes that transfer data between the system ASIC and the Si5540. High Speed Clock Disable. When this input is high, the output driver for TXCLKOUT is disabled. In applications that do not require the output data clock, the output clock driver should be disabled to save power. High Speed Clock Output. The high speed output clock, TXCLKOUT, is generated by the PLL in the clock multiplier unit. It's frequency is nominally 16 or 64 times the selected reference source. Differential Parallel Data Input. The 16-bit data word present on these pins is multiplexed into a high speed serial stream and output on TXDOUT. The data on these inputs is clocked into the device by the rising edge of TXCLKIN. Differential High Speed Data Output. The 16-bit word input on TXDIN[15:0] is multiplexed into a high speed serial stream that is output on these pins. This output is updated by the rising edge of TXCLKOUT. CMU Loss-of-Lock. The output is asserted low when the CMU is not phase locked to the selected reference source.
K3-4
O
LVDS
B4
TXCLKDSBL
I
LVTTL
C1, D1
TXCLKOUT+, TXCLKOUT-
O
CML
A7-10, B5-10, C9-10, D9-10, E9-10, F9-10, G9-10, H9-10, J5-10, K7-10 F1, G1
TXDIN[15:0]-, TXDIN[15:0]+
I
LVDS
TXDOUT+, TXDOUT-
O
CML
J2
TXLOL
O
LVTTL
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Si 5540
Pin Number(s) Pin Name I/O Signal Level Description Data Bus Transmit Order. For TXMSBSEL = 0, data on TXDIN[0] is transmitted first followed by TXDIN[1] through TXDIN[15]. For TXMSBSEL = 1, TXDIN[15] is transmitted first followed by TXDIN[14] through TXDIN[0]. Transmit Data Squelch. If TXSQLCH is asserted low, the output data stream on TXDOUT will be forced to 0. If TXSQLCH = 1, TX squelching is turned off. Supply Voltage. Nominally 1.8 V.
J4
TXMSBSEL
I
LVTTL
A4
TXSQLCH
I
LVTTL
D4-7, E4-7, F4-7, G4-7, C3
VDD VDD33
VDD VDD33
1.8 V
1.8 V or 3.3 V Digital Output Supply. Must be tied to either 1.8 V or 3.3 V. When tied to 3.3 V, LVTTL compatible output voltage swings on TXLOL and FIFOERR are supported.
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Si5540
Ordering Guide
Table 7. Ordering Guide Part Number Package Temperature
SI5540-BC
99 BGA
-40C to 85C
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17
Si 5540
Package Outline
Figure 7 illustrates the package details for the Si5540. Table 8 lists the values for the dimensions shown in the illustration.
A1 Ball Pad Corner A D A1
10 9 8 7 6 5 4 3 2 1
A1 Ball Pad Corner
e
A B C D
E b 1.00 Ref
E F G H J K
1.00 Ref A2 Seating Plane
e
Top View
Side View
Bottom View
Figure 7. 99-Ball Grid Array (BGA)
Table 8. Package Diagram Dimensions
Symbol Min 1.30 0.31 0.65 -- -- -- -- Millimeters Nom 1.40 0.36 0.70 0.46 11.00 11.00 1.00 Max 1.50 0.41 0.75 -- -- -- --
A A1 A2 b D E e
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Si5540 NOTES:
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Si 5540
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, SiPHY, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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